1. Field of the Invention
The present invention relates to data transfer, and more particularly to a system and method for transferring data via a synchronous to asynchronous to synchronous interface which behaves in a reliable manner and is adaptable for multiple frequencies of operation.
2. Description of the Related Art
Interlocked Pipelined complementary metal oxide semiconductor (IPCMOS) circuits and techniques are disclosed in U.S. Pat. No. 6,182,233, incorporated herein by reference. A paper describing the results of an implementation of these IPCMOS circuits on a test site is found in an article published in the ISSCC 2000 Digest of Technical Papers, Session 17, Logic and Systems, Paper WA 17.3, by Schuster et al. entitled “Asynchronous Interlocked Pipelined CMOS Circuits at 3.3-4.5 GHz”, incorporated herein by reference and hereinafter referred to as the ISSCC paper. In the ISSCC paper, asynchronous interlocked locally generated clocks drive a path through a 3 to 2 compressor tree of a Floating Point Multiplier (FPM) at frequencies as fast as 4.5 GHz in a 0.18 micron 1.5 Volt bulk CMOS technology. Power reductions greater than two times are estimated with these IPCMOS techniques.
In U.S. patent application Ser. No. 6,182,233 referenced above, circuits and techniques are disclosed for asynchronously interlocking blocks in the forward and reverse directions that have extremely small overhead for handshaking. This makes very high performance possible.
Synchronous pipelines are typically subject to clock slew problems which may cause undesirable delays in the pipelines. It would be advantageous to replace portions of existing synchronous designs with asynchronous clocks and circuits to achieve higher performance and lower power. However, interfaces between a synchronous portion of the system and an asynchronous portion may be difficult to implement.
Therefore, a need exists for interfaces that make it possible to go from a synchronous mode of operation to an asynchronous mode of operation and then back to a synchronous mode in a reliable manner and at different frequencies. A further need exists for implementing circuits and timing concepts needed to provide these synchronous to asynchronous to synchronous interfaces.